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<title>CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value </title></head>
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<h1>CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>F3 0F 5A /r CVTSS2SD xmm1, xmm2/m32</td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Convert one single-precision floating-point value in xmm2/m32 to one double-precision floating-point value in xmm1.</td></tr>
<tr>
<td>VEX.NDS.128.F3.0F.WIG 5A /r VCVTSS2SD xmm1, xmm2, xmm3/m32</td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Convert one single-precision floating-point value in xmm3/m32 to one double-precision floating-point value and merge with high bits of xmm2.</td></tr>
<tr>
<td>EVEX.NDS.LIG.F3.0F.W0 5A /r VCVTSS2SD xmm1 {k1}{z}, xmm2, xmm3/m32{sae}</td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Convert one single-precision floating-point value in xmm3/m32 to one double-precision floating-point value and merge with high bits of xmm2 under writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>T1S</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Converts a single-precision floating-point value in the “convert-from” source operand to a double-precision floating-point value in the destination operand. When the “convert-from” source operand is an XMM register, the single-precision floating-point value is contained in the low doubleword of the register. The result is stored in the low quadword of the destination operand.</p>
<p>128-bit Legacy SSE version: The “convert-from” source operand (the second operand) is an XMM register or memory location. Bits (MAX_VL-1:64) of the corresponding destination register remain unchanged. The destina-tion operand is an XMM register.</p>
<p>VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be an XMM register or a 32-bit memory location. The first source and destination operands are XMM registers. Bits (127:64) of the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.</p>
<p>Software should ensure VCVTSS2SD is encoded with VEX.L=0. Encoding VCVTSS2SD with VEX.L=1 may encounter unpredictable behavior across different processor generations.</p>
<h2>Operation</h2>
<p><strong>VCVTSS2SD (EVEX encoded version)</strong></p>
<pre>IF k1[0] or *no writemask*
    THEN
              DEST[63:0] (cid:197) Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0]);
    ELSE
         IF *merging-masking*
                                                    ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE
                                                    ; zeroing-masking
                    THEN DEST[63:0] = 0
         FI;
FI;
DEST[127:64] (cid:197) SRC1[127:64]
DEST[MAX_VL-1:128] (cid:197) 0</pre>
<p><strong>VCVTSS2SD (VEX.128 encoded version)</strong></p>
<pre>DEST[63:0] (cid:197)Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0])
DEST[127:64] (cid:197)SRC1[127:64]
DEST[MAX_VL-1:128] (cid:197)0</pre>
<p><strong>CVTSS2SD (128-bit Legacy SSE version)</strong></p>
<pre>DEST[63:0] (cid:197)Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]);
DEST[MAX_VL-1:64] (Unmodified)</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>VCVTSS2SD __m128d _mm_cvt_roundss_sd(__m128d a, __m128 b, int r);</p>
<p>VCVTSS2SD __m128d _mm_mask_cvt_roundss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b, int r);</p>
<p>VCVTSS2SD __m128d _mm_maskz_cvt_roundss_sd(__mmask8 k, __m128d a, __m128 a, int r);</p>
<p>VCVTSS2SD __m128d _mm_mask_cvtss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b);</p>
<p>VCVTSS2SD __m128d _mm_maskz_cvtss_sd(__mmask8 m, __m128d a,__m128 b);</p>
<p>CVTSS2SD __m128d_mm_cvtss_sd(__m128d a, __m128 a);</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>Invalid, Denormal</p>
<h2>Other Exceptions</h2>
<table class="exception-table">
<tr>
<td>VEX-encoded instructions, see Exceptions Type 3.</td></tr>
<tr>
<td>EVEX-encoded instructions, see Exceptions Type E3.</td></tr></table></body></html>